Logic Analyzer
Last updated
Last updated
The default FPGA configuration implements a Logic Analyzer compatible with Sigrok Pulseview. This logic analyzer uses the FPGA front end and communicates with the PC using the FTDI High speed user interface. The Logic Analyzer operates transparently to the IO features of Free Wili so you can use it to test when you are interfacing to digital protocols.
The FPGA bit files for the logic analyzer are always being implemented and are open source. These are available at the Free Wili github. You can change the default FPGA bit file in the settings of FreeWili.
